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LPC1102
Rev. 00.04 -- 23 June 2010
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32-bit ARM Cortex-M0 microcontroller; 32 kB flash and 8 kB SRAM
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1. General description
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The LPC1102 is an ARM Cortex-M0 based, low-cost 32-bit MCU, designed for 8/16-bit microcontroller applications, offering performance, low power, simple instruction set and memory addressing together with reduced code size compared to existing 8/16-bit architectures. The LPC1102 operates at CPU frequencies of up to 50 MHz. The peripheral complement of the LPC1102 includes 32 kB of flash memory, 8 kB of data memory, one RS-485/EIA-485 UART, one SPI interface with SSP features, four general purpose counter/timers, a 10-bit ADC, and 11 general purpose I/O pins.
2. Features and benefits
System: ARM Cortex-M0 processor, running at frequencies of up to 50 MHz. ARM Cortex-M0 built-in Nested Vectored Interrupt Controller (NVIC). Serial Wire Debug. System tick timer. Memory: 32 kB on-chip flash programming memory. 8 kB SRAM. In-Application Programming (IAP) and In-System Programming (ISP) support via on-chip bootloader software. Digital peripherals: 11 General Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors. GPIO pins can be used as edge and level sensitive interrupt sources. Four general purpose counter/timers with a total of one capture input and nine match outputs. Programmable WatchDog Timer (WDT). Analog peripherals: 10-bit ADC with input multiplexing among five pins.
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Serial interfaces: UART with fractional baud rate generation, internal FIFO, and RS-485 support. One SPI controller with SSP features and with FIFO and multi-protocol capabilities (see Section 7.16). Clock generation: 12 MHz internal RC oscillator trimmed to 1% accuracy that can optionally be used as a system clock. Programmable watchdog oscillator with a frequency range of 7.8 kHz to 1.8 MHz. PLL allows CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. May be run from an external clock or the internal RC oscillator. Clock output function with divider that can reflect the external clock, IRC clock, CPU clock, and the Watchdog clock. Power control: Integrated PMU (Power Management Unit) to minimize power consumption during Sleep and Deep-sleep modes. Two reduced power modes: Sleep and Deep-sleep modes. Processor wake-up from Deep-sleep mode via a dedicated start logic using up to six of the functional pins. Power-On Reset (POR). Brownout detect with four separate thresholds for interrupt and forced reset. Unique device serial number for identification. Single 3.3 V power supply (1.8 V to 3.6 V). Available as WLCSP16 package.
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3. Applications
Mobile devices Consumer peripherals Lighting 8-/16-bit applications Portable devices
4. Ordering information
Table 1. Ordering information Package Name LPC1102 WLCSP16 Description wafer level chip-size package; 16 bumps; 2.17 x 2.32 x 0.6 mm Version Type number
4.1 Ordering options
Table 2. Ordering options Flash 32 kB Total SRAM 8 kB UART RS-485 1 SPI 1 ADC channels 5 Package WLCSP16 Type number LPC1102
LPC1102
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5. Block diagram
XTALIN
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SWD
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RESET
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LPC1102
IRC TEST/DEBUG INTERFACE CLOCK GENERATION, POWER CONTROL, SYSTEM FUNCTIONS clocks and controls FLASH 32 kB slave GPIO port PIO0/1 HIGH-SPEED GPIO slave AHB-LITE BUS SRAM 8 kB slave slave
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POR
ARM CORTEX-M0
system bus
ROM
slave AHB TO APB BRIDGE RXD TXD UART 10-bit ADC AD[4:0] SCK, MISO, MOSI
SPI CT32B0_MAT[3,1,0] CT32B1_MAT[2:0] CT32B1_CAP0 CT16B0_MAT[2:0] 32-bit COUNTER/TIMER 0 WDT 32-bit COUNTER/TIMER 1 IOCONFIG 16-bit COUNTER/TIMER 0 16-bit COUNTER/TIMER 1 SYSTEM CONTROL PMU
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Fig 1.
LPC1102 block diagram
LPC1102
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6. Pinning information
6.1 Pinning
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B
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1 ball A1 index area
2
3
4
Fig 2.
Pin configuration WLCSP16 package
6.2 Pin description
Table 3. Symbol LPC1102 pin description table Pin Type Reset Wake-up state[1] function
[2]
Description
RESET/PIO0_0
C1[3]
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RESET -- External reset input: A LOW on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0. PIO0_0 -- General purpose digital input/output pin. PIO0_8 -- General purpose digital input/output pin. MISO0 -- Master In Slave Out for SPI. CT16B0_MAT0 -- Match output 0 for 16-bit timer 0. PIO0_9 -- General purpose digital input/output pin. MOSI0 -- Master Out Slave In for SPI. CT16B0_MAT1 -- Match output 1 for 16-bit timer 0. SWCLK -- Serial wire clock. PIO0_10 -- General purpose digital input/output pin. SCK -- Serial clock for SPI. CT16B0_MAT2 -- Match output 2 for 16-bit timer 0. R -- Reserved. PIO0_11 -- General purpose digital input/output pin. AD0 -- A/D converter, input 0. CT32B0_MAT3 -- Match output 3 for 32-bit timer 0.
I/O PIO0_8/MISO/ CT16B0_MAT0 A2[4] I/O I/O O PIO0_9/MOSI/ CT16B0_MAT1 A3[4] I/O I/O O SWCLK/ PIO0_10/ SCK/CT16B0_MAT2 A4[4] I I/O I/O O R/PIO0_11/ AD0/CT32B0_MAT3 B4[5] I/O I I
I; PU I; PU I; PU I; PU -
DS DS DS DS DS DS DS DS DS DS DS DS DS DS DS
LPC1102
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Table 3. Symbol
LPC1102 pin description table ...continued Pin Type Reset Wake-up state[1] function
[2]
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Description
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R/PIO1_0/ AD1/CT32B1_CAP0
B3[5]
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I/O I I
I; PU I; PU I; PU I; PU I; PU I; PU -
DS DS DS DS -
R -- Reserved. PIO1_0 -- General purpose digital input/output pin. AD1 -- A/D converter, input 1. CT32B1_CAP0 -- Capture input 0 for 32-bit timer 1. R -- Reserved. PIO1_1 -- General purpose digital input/output pin. AD2 -- A/D converter, input 2. CT32B1_MAT0 -- Match output 0 for 32-bit timer 1. R -- Reserved. PIO1_2 -- General purpose digital input/output pin. AD3 -- A/D converter, input 3. CT32B1_MAT1 -- Match output 1 for 32-bit timer 1. SWDIO -- Serial wire debug input/output. PIO1_3 -- General purpose digital input/output pin. AD4 -- A/D converter, input 4. CT32B1_MAT2 -- Match output 2 for 32-bit timer 1. PIO1_6 -- General purpose digital input/output pin. RXD -- Receiver input for UART. CT32B0_MAT0 -- Match output 0 for 32-bit timer 0. PIO1_7 -- General purpose digital input/output pin. TXD -- Transmitter output for UART. CT32B0_MAT1 -- Match output 1 for 32-bit timer 0.
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R/PIO1_1/ AD2/CT32B1_MAT0
C4[5]
I/O I O
R/PIO1_2/ AD3/CT32B1_MAT1
C3[5]
I/O I O
SWDIO/PIO1_3/AD4/ CT32B1_MAT2
D4[5]
I/O I/O I O
PIO1_6/RXD/ CT32B0_MAT0
C2[4]
I/O I O
PIO1_7/TXD/ CT32B0_MAT1
D1[4]
I/O O O
VDD XTALIN VSS
[1] [2] [3] [4] [5] [6]
D2; A1 I B2[6] I
3.3 V supply voltage to the internal regulator, the external rail, and the ADC. Also used as the ADC reference voltage. External clock input and input to internal clock generator circuits. Input voltage must not exceed 1.8 V. Ground.
D3; B1 I
Pin state at reset for default function: I = Input; PU = internal pull-up enabled. Wake-up functionality: DS = Deep-sleep mode wake-up pin (to be configured in the start logic). See Figure 20 for the reset pad configuration. 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see Figure 19). 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input. When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant (see Figure 19). When the external clock is not used, connect XTALIN as follows: XTALIN can be left floating or can be grounded (grounding is preferred to reduce susceptibility to noise).
LPC1102
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7. Functional description
7.1 ARM Cortex-M0 processor
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The ARM Cortex-M0 is a general purpose, 32-bit microprocessor, which offers high performance and very low power consumption.
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7.2 On-chip flash program memory
The LPC1102 contain 32 kB of on-chip flash memory. Remark: The LPC1102 supports In-Application Programming (IAP) and In-System Programming (ISP). For ISP, since there is no dedicated ISP entry pin, user code is required to invoke ISP functionality. Unprogrammed parts will automatically boot into ISP mode.
7.3 On-chip SRAM
The LPC1102 contain 8 on-chip static RAM memory.
7.4 Memory map
The LPC1102 incorporates several distinct memory regions, shown in the following figures. Figure 3 shows the overall map of the entire address space from the user program viewpoint following reset. The interrupt vector area supports address remapping. The AHB peripheral area is 2 megabyte in size, and is divided to allow for up to 128 peripherals. The APB peripheral area is 512 kB in size and is divided to allow for up to 32 peripherals. Each peripheral of either type is allocated 16 kilobytes of space. This allows simplifying the address decoding for each peripheral.
LPC1102
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AHB peripherals 0xFFFF FFFF reserved 0xE010 0000 private peripheral bus reserved 0x5020 0000 AHB peripherals 0x5000 0000 0xE000 0000 15-12 11-8 7-4 3-0 reserved reserved reserved GPIO PIO1 GPIO PIO0 APB peripherals 31 - 23 reserved 0x4008 0000 1 GB APB peripherals 0x4000 0000 22 0x4005 C000 reserved 21 - 19 reserved 0x4004 C000 18 reserved 17 16 15 0.5 GB reserved 0x1FFF 4000 16 kB boot ROM reserved 0x1FFF 0000 9 8 7 6 0x1000 2000 8 kB SRAM reserved 0x1000 0000 5 4 3 2 1 0 + 512 byte 0x0000 8000 32 kB on-chip flash 0 GB 0x0000 0000
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4 GB
LPC1102
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0x5020 0000
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127 - 16 reserved 0x5004 0000 0x5003 0000 0x5002 0000 0x5001 0000 0x5000 0000 0x4008 0000
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0x4005 8000
system control IOCONFIG SPI flash controller PMU 13 - 10 reserved
0x4004 8000 0x4004 4000 0x4004 0000 0x4003 C000 0x4003 8000
0x2000 0000
14
0x4002 8000 reserved reserved ADC 32-bit counter/timer 1 32-bit counter/timer 0 16-bit counter/timer 1 16-bit counter/timer 0 UART WDT reserved 0x0000 0200 0x0000 0000 0x4002 4000 0x4002 0000 0x4001 C000 0x4001 8000 0x4001 4000 0x4001 0000 0x4000 C000 0x4000 8000 0x4000 4000 0x4000 0000
active interrupt vectors
Fig 3.
LPC1102 memory map
7.5 Nested Vectored Interrupt Controller (NVIC)
The Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M0. The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts.
7.5.1 Features
* Controls system exceptions and peripheral interrupts. * In the LPC1102, the NVIC supports 19 vectored interrupts including up to 6 inputs to
the start logic from individual GPIO pins.
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* Four programmable interrupt priority levels, with hardware priority level masking. * Relocatable vector table. * Software interrupt generation.
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7.5.2 Interrupt sources
Each peripheral device has one interrupt line connected to the NVIC but may have several interrupt flags. Individual interrupt flags may also represent more than one interrupt source. Any GPIO pin (total of up to 11 pins) regardless of the selected function, can be programmed to generate an interrupt on a level, or rising edge or falling edge, or both.
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7.6 IOCONFIG block
The IOCONFIG block allows selected pins of the microcontroller to have more than one function. Configuration registers control the multiplexers to allow connection between the pin and the on-chip peripherals. Peripherals should be connected to the appropriate pins prior to being activated and prior to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is not mapped to a related pin should be considered undefined.
7.7 Fast general purpose parallel I/O
Device pins that are not connected to a specific peripheral function are controlled by the GPIO registers. Pins may be dynamically configured as inputs or outputs. Multiple outputs can be set or cleared in one write operation. LPC1102 use accelerated GPIO functions:
* GPIO registers are a dedicated AHB peripheral so that the fastest possible I/O timing
can be achieved.
* Entire port value can be written in one instruction.
Additionally, any GPIO pin (total of 11 pins) providing a digital function can be programmed to generate an interrupt on a level, a rising or falling edge, or both.
7.7.1 Features
* Bit level port registers allow a single instruction to set or clear any number of bits in
one write operation.
* Direction control of individual bits. * All I/O default to inputs with pull-ups enabled after reset. * Pull-up/pull-down resistor configuration can be programmed through the IOCONFIG
block for each GPIO pin.
7.8 UART
The LPC1102 contains one UART. Support for RS-485/9-bit mode allows both software address detection and automatic address detection using 9-bit mode.
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The UART includes a fractional baud rate generator. Standard baud rates such as 115200 Bd can be achieved with any crystal frequency above 2 MHz.
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7.8.1 Features
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Maximum UART data bit rate of 3.125 MBit/s. 16 Byte Receive and Transmit FIFOs. Register locations conform to 16C550 industry standard. Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B. Built-in fractional baud rate generator covering wide range of baud rates without a need for external crystals of particular values.
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* FIFO control mechanism that enables software flow control implementation. * Support for RS-485/9-bit mode. 7.9 SPI serial I/O controller
The LPC1102 contains one SPI controller and fully supports SSP features. The SPI controller is capable of operation on a SSP, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus. Only a single master and a single slave can communicate on the bus during a given data transfer. The SPI supports full duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the slave and from the slave to the master. In practice, often only one of these data flows carries meaningful data. Remark: Care must be taken when using the SPI because the SPI clock SCK and the serial wire debug clock SWCLK share the same pin on the WLCSP16 package. Once the SPI is enabled, the serial wire debugger is no longer available.
7.9.1 Features
* Maximum SPI speed of 25 Mbit/s (master) or 4.17 Mbit/s (slave) (in SSP mode) * Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National
Semiconductor Microwire buses
* * * *
Synchronous serial communication Master or slave operation 8-frame FIFOs for both transmit and receive 4-bit to 16-bit frame
7.10 10-bit ADC
The LPC1102 contains one ADC. It is a single 10-bit successive approximation ADC with eight channels.
7.10.1 Features
* 10-bit successive approximation ADC. * Input multiplexing among 5 pins. * Power-down mode.
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* * * * *
Measurement range 0 V to VDD. 10-bit conversion time 2.44 s. Burst conversion mode for single or multiple inputs. Optional conversion on transition of input pin or timer match signal.
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Individual result registers for each ADC channel to reduce interrupt overhead.
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7.11 General purpose external event counter/timers
The LPC1102 includes two 32-bit counter/timers and two 16-bit counter/timers. The counter/timer is designed to count cycles of the system derived clock. It can optionally generate interrupts or perform other actions at specified timer values, based on four match registers. Each counter/timer also includes one capture input to trap the timer value when an input signal transitions, optionally generating an interrupt.
7.11.1 Features
* A 32-bit/16-bit timer/counter with a programmable 32-bit/16-bit prescaler. * Counter or timer operation. * One capture channel that can take a snapshot of the timer value when an input signal
transitions. A capture event may also generate an interrupt.
* Four match registers per timer that allow:
- Continuous operation with optional interrupt generation on match. - Stop timer on match with optional interrupt generation. - Reset timer on match with optional interrupt generation.
* Up to four external outputs corresponding to match registers, with the following
capabilities: - Set LOW on match. - Set HIGH on match. - Toggle on match. - Do nothing on match.
7.12 System tick timer
The ARM Cortex-M0 includes a system tick timer (SYSTICK) that is intended to generate a dedicated SYSTICK exception at a fixed time interval (typically 10 ms).
7.13 Watchdog timer
The purpose of the watchdog is to reset the microcontroller within a selectable time period.
7.13.1 Features
* Internally resets chip if not periodically reloaded. * Debug mode. * Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be
disabled.
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* * * *
Incorrect/Incomplete feed sequence causes reset/interrupt if enabled. Flag to indicate watchdog reset. Programmable 32-bit timer with internal prescaler.
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Selectable time period from (Tcy(WDCLK) x 256 x 4) to (Tcy(WDCLK) x 232 x 4) in multiples of Tcy(WDCLK) x 4.
* The Watchdog Clock (WDCLK) source can be selected from the Internal RC oscillator
(IRC), the Watchdog oscillator, or the main clock. This gives a wide range of potential timing choices of Watchdog operation under different power reduction conditions. It also provides the ability to run the WDT from an entirely internal source that is not dependent on an external crystal and its associated components and wiring for increased reliability.
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7.14 Clocking and power control
7.14.1 Crystal oscillators
The LPC1102 include two independent oscillators. These are the Internal RC oscillator (IRC) and the Watchdog oscillator. Each oscillator can be used for more than one purpose as required in a particular application. Following reset, the LPC1102 will operate from the Internal RC oscillator until switched by software. This allows systems to operate without any external crystal and the bootloader code to operate at a known frequency. See Figure 4 for an overview of the LPC1102 clock generation.
LPC1102
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32-bit ARM Cortex-M0 microcontroller
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SYSTEM CLOCK DIVIDER
system clock
AHB clock 0 (system)
A
A F R
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18
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AHB clocks 1 to 18 (memories and peripherals)
AHBCLKCTRL[1:18] (AHB clock enable)
IRC oscillator
SPI0 PERIPHERAL CLOCK DIVIDER main clock UART PERIPHERAL CLOCK DIVIDER
SPI0
watchdog oscillator
UART
MAINCLKSEL (main clock select) IRC oscillator SYSTEM PLL external clock
IRC oscillator WDT CLOCK DIVIDER watchdog oscillator WDTUEN (WDT clock update enable) WDT
SYSPLLCLKSEL (system PLL clock select)
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Fig 4.
LPC1102 clock generation block diagram
7.14.1.1
Internal RC oscillator The IRC may be used as the clock source for the WDT, and/or as the clock that drives the PLL and subsequently the CPU. The nominal IRC frequency is 12 MHz. The IRC is trimmed to 1 % accuracy over the entire voltage and temperature range. Upon power-up or any chip reset, the LPC1102 use the IRC as the clock source. Software may later switch to one of the other available clock sources.
7.14.1.2
Watchdog oscillator The watchdog oscillator can be used as a clock source that directly drives the CPU or the watchdog timer. The watchdog oscillator nominal frequency is programmable between 7.8 kHz and 1.7 MHz. The frequency spread over processing and temperature is 40%.
7.14.2 System PLL
The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input frequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO). The multiplier can be an integer value from 1 to 32. The CCO operates in the range of 156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO within its frequency range while the PLL is providing the desired output frequency. The output divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. Since the
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minimum output divider value is 2, it is insured that the PLL output has a 50 % duty cycle. The PLL is turned off and bypassed following a chip reset and may be enabled by software. The program must configure and activate the PLL, wait for the PLL to lock, and then connect to the PLL as a clock source. The PLL settling time is 100 s.
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7.14.3 Wake-up process
The LPC1102 begin operation at power-up by using the 12 MHz IRC oscillator as the clock source. This allows chip operation to resume quickly. If an external clock or the PLL is needed by the application, software will need to enable these features and wait for them to stabilize before they are used as a clock source.
A FT D R A
7.14.4 Power control
The LPC1102 support a variety of power control features. There are two special modes of processor power reduction: Sleep mode and Deep-sleep mode. The CPU clock rate may also be controlled as needed by changing clock sources, reconfiguring PLL values, and/or altering the CPU clock divider value. This allows a trade-off of power versus processing speed based on application requirements. In addition, a register is provided for shutting down the clocks to individual on-chip peripherals, allowing fine tuning of power consumption by eliminating all dynamic power use in any peripherals that are not required for the application. Selected peripherals have their own clock divider which provides even better power control. 7.14.4.1 Sleep mode When Sleep mode is entered, the clock to the core is stopped. Resumption from the Sleep mode does not need any special sequence but re-enabling the clock to the ARM core. In Sleep mode, execution of instructions is suspended until either a reset or interrupt occurs. Peripheral functions continue operation during Sleep mode and may generate interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic power used by the processor itself, memory systems and related controllers, and internal buses. 7.14.4.2 Deep-sleep mode In Deep-sleep mode, the chip is in Sleep mode, and in addition all analog blocks are shut down except for the watchdog oscillator and the BOD circuit, which can be configured to remain running in Deep-sleep mode to allow a reset initiated by a timer or BOD event. Deep-sleep mode allows for additional power savings. The GPIO pins (6 pins total, see Table 3) serve as external wake-up pins to a dedicated start logic to wake up the chip from Deep-sleep mode. The clock source should be switched to IRC before entering Deep-sleep mode unless the watchdog oscillator remains running in Deep-sleep mode. The IRC can be switched on and off glitch-free and provides a clean clock signal after start-up.
LPC1102
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D
D
D R A FT
D R A FT
NXP Semiconductors
LPC1102
FT FT D D R R A A FT FT D D R R A A FT FT D D
D R A
R
R A
A FT
32-bit ARM Cortex-M0 microcontroller
FT D R A
D R A
D R A FT D R FT
7.15 System control
7.15.1 Reset
D
R
Reset has four sources on the LPC1102: the RESET pin, the Watchdog reset, power-on reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt trigger input pin. Assertion of chip reset by any source, once the operating voltage attains a usable level, starts the IRC and initializes the flash controller. When the internal Reset is removed, the processor begins executing at address 0, which is initially the Reset vector mapped from the boot block. At that point, all of the processor and peripheral registers have been initialized to predetermined values.
D
R A FT D R
R A F D R A FT
A FT A FT R A
D FT D R A
7.15.2 Brownout detection
The LPC1102 includes four levels for monitoring the voltage on the VDD pin. If this voltage falls below one of the four selected levels, the BOD asserts an interrupt signal to the NVIC. This signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC in order to cause a CPU interrupt; if not, software can monitor the signal by reading a dedicated status register. Four additional threshold levels can be selected to cause a forced reset of the chip.
7.15.3 Code security (Code Read Protection - CRP)
This feature of the LPC1102 allows user to enable different levels of security in the system so that access to the on-chip flash and use of the Serial Wire Debugger (SWD) can be restricted. When needed, CRP is invoked by programming a specific pattern into a dedicated flash location. IAP commands are not affected by the CRP. There are three levels of Code Read Protection: 1. CRP1 disables access to the chip via the SWD and allows partial flash update (excluding flash sector 0). This mode is useful when CRP is required and flash field updates are needed but all sectors can not be erased. 2. CRP2 disables access to the chip via the SWD and only allows full flash erase and update. 3. Running an application with level CRP3 selected fully disables any access to the chip via the SWD pins. Remark: The LPC1102 does not provide an ISP entry pin to be monitored at reset. For all three CRP levels, the user's application code must provide a flash update mechanism which reinvokes ISP by defining a user-selected PIO pin for ISP entry.
CAUTION If Code Read Protection (CRP1/2/3) is selected, no future factory testing can be performed on the device.
7.15.4 APB interface
The APB peripherals are located on one APB bus.
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D
D R A FT
D R A FT
NXP Semiconductors
LPC1102
FT FT D D R R A A FT FT D D R R A A FT FT D D
D R A
R
R A
A FT
32-bit ARM Cortex-M0 microcontroller
FT D R A
D R A
D R A FT D R FT
7.15.5 AHBLite
D
R
The AHBLite connects the CPU bus of the ARM Cortex-M0 to the flash memory, the main static RAM, and the Boot ROM.
D R A FT D
R A FT
R A F D R A FT D
A FT
7.15.6 External interrupt inputs
All GPIO pins can be level or edge sensitive interrupt inputs.
R A FT D R A
7.15.7 Memory mapping control
The Cortex-M0 incorporates a mechanism that allows remapping the interrupt vector table to alternate locations in the memory map. This is controlled via the Vector Table Offset Register contained in the NVIC. The vector table may be located anywhere within the bottom 1 GB of Cortex-M0 address space. The vector table must be located on a 128 word (512 byte) boundary.
7.16 Emulation and debugging
Debug functions are integrated into the ARM Cortex-M0. Serial wire debug with four breakpoints and two watchpoints is supported. Remark: Care must be taken when using the SPI because the SPI clock SCK and the serial wire debug clock SWCLK share the same pin on the WLCSP16 package. Once the SPI is enabled, the serial wire debugger is no longer available.
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D
D R A FT
D R A FT
NXP Semiconductors
LPC1102
FT FT D D R R A A FT FT D D R R A A FT FT D D
D R A
R
R A
A FT
32-bit ARM Cortex-M0 microcontroller
FT D R A
D R A
D R A FT D R FT
8. Limiting values
Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol VDD VI Parameter supply voltage (core and external rail) input voltage 5 V tolerant I/O pins; only valid when the VDD supply voltage is present per supply pin per ground pin -(0.5VDD) < VI < (1.5VDD); Tj < 125 C Tstg Tj(max) Ptot(pack) storage temperature maximum junction temperature total power dissipation (per package) based on package heat transfer, not device power consumption human body model; all pins
[5] [4] [2]
D
R
R A FT D R
R A F D R A FT
A FT A FT D
D
Conditions
Min 1.8 -0.5
Max 3.6 +5.5
Unit V V
R A FT D R A
IDD ISS Ilatch
supply current ground current I/O latch-up current
[3] [3]
-
100 100 100
mA mA mA
-65 -
+150 150 1.5
C C W
VESD
electrostatic discharge voltage
-6500
+6500
V
[1]
The following applies to the limiting values: a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted.
[2] [3] [4] [5]
Including voltage on outputs in 3-state mode. The peak current is limited to 25 times the corresponding maximum current. Dependent on package type. Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor.
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D
D R A FT
D R A FT
NXP Semiconductors
LPC1102
FT FT D D R R A A FT FT D D R R A A FT FT D D
D R A
R
R A
A FT
32-bit ARM Cortex-M0 microcontroller
FT D R A
D R A
D R A FT D R FT
9. Static characteristics
Table 5. Static characteristics Tamb = -40 C to +85 C, unless otherwise specified. Symbol VDD IDD Parameter supply voltage (core and external rail) supply current Active mode; code Conditions Min 1.8 Typ[1] 3.3
D
R
Max 3.6
R A FT D R
R A F D R A FT
A FT A
Unit V
FT D R A
D FT D R A
while(1){}
executed from flash system clock = 12 MHz VDD = 3.3 V system clock = 50 MHz VDD = 3.3 V Sleep mode; system clock = 12 MHz VDD = 3.3 V Deep-sleep mode; VDD = 3.3 V Standard port pins, RESET IIL IIH LOW-level input current VI = 0 V; on-chip pull-up resistor disabled HIGH-level input current OFF-state output current input voltage output voltage HIGH-level input voltage LOW-level input voltage hysteresis voltage HIGH-level output voltage 2.0 V VDD 3.6 V; IOH = -4 mA 1.8 V VDD < 2.0 V; IOH = -3 mA VOL LOW-level output voltage 2.0 V VDD 3.6 V; IOL = 4 mA 1.8 V VDD < 2.0 V; IOL = 3 mA IOH HIGH-level output current VOH = VDD - 0.4 V; 2.0 V VDD 3.6 V 1.8 V VDD < 2.0 V -3 mA VI = VDD; on-chip pull-down resistor disabled VO = 0 V; VO = VDD; on-chip pull-up/down resistors disabled pin configured to provide a digital function output active
[9][10] [2][3][8] [2][3][4] [5][6] [2][3][5] [6][7] [2][3][4] [5][6]
-
2 7 1
-
mA mA mA
-
2
-
A
-
0.5 0.5
10 10
nA nA
IOZ
-
0.5
10
nA
VI VO VIH VIL Vhys VOH
0 0 0.7VDD VDD - 0.4 VDD - 0.4 -4
0.4 -
5.0 VDD 0.3VDD 0.4 0.4 -
V V V V V V V V V mA
LPC1102
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D
D R A FT
D R A FT
NXP Semiconductors
LPC1102
FT FT D D R R A A FT FT D D R R A A FT FT D D
D R A
R
R A
A FT
32-bit ARM Cortex-M0 microcontroller
FT D R A
D R A
D R A FT D R FT
Table 5. Static characteristics ...continued Tamb = -40 C to +85 C, unless otherwise specified. Symbol IOL Parameter LOW-level output current Conditions VOL = 0.4 V 2.0 V VDD 3.6 V 1.8 V VDD < 2.0 V IOHS IOLS Ipd Ipu HIGH-level short-circuit VOH = 0 V output current LOW-level short-circuit output current pull-down current pull-up current VOL = VDD VI = 5 V VI = 0 V; 2.0 V VDD 3.6 V 1.8 V VDD < 2.0 V VDD < VI < 5 V External clock input Vi(xtal)
[1] [2] [3] [4] [5] [6] [7] [8] [9]
[11]
D
R
R A FT
R A F
A FT
Min 4 3 10 -15 -10 0 -0.5
Typ[1] 50 -50 -50 0 1.8
Max -45 50 150 -85 -85 0 1.95
Unit mA
D
D R
R A FT D A FT D R A
A
mA mA mA A A A A V
FT D R
[11]
crystal input voltage
Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. Tamb = 25 C. IDD measurements were performed with all pins configured as GPIO outputs driven LOW and pull-up resistors disabled. IRC enabled; external clock disabled; system PLL disabled. BOD disabled. All peripherals disabled in the SYSAHBCLKCTRL register. Peripheral clocks to UART and SPI0/1 disabled in system configuration block. ; system PLL enabled. All oscillators and analog blocks turned off in the PDSLEEPCFG register; PDSLEEPCFG = 0x0000 18FF. Including voltage on outputs in 3-state mode.
[10] VDD supply voltage must be present. [11] Allowed as long as the current limit does not exceed the maximum current allowed by the device. [12] To VSS.
Table 6. ADC static characteristics Tamb = -40 C to +85 C unless otherwise specified; ADC frequency 4.5 MHz, VDD = 2.5 V to 3.6 V. Symbol VIA Cia ED EL(adj) EO EG ET Rvsi Ri
[1]
Parameter analog input voltage analog input capacitance differential linearity error integral non-linearity offset error gain error absolute error voltage source interface resistance input resistance
Conditions
Min 0 [1][2] [3] [4] [5] [6]
Typ -
Max VDD 1 1 1.5 3.5 0.6 4 40 2.5
Unit V pF LSB LSB LSB % LSB k M
-
[7][8]
-
The ADC is monotonic, there are no missing codes.
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D
D R A FT
D R A FT
NXP Semiconductors
LPC1102
FT FT D D R R A A FT FT D D R R A A FT FT D D
D R A
R
R A
A FT
32-bit ARM Cortex-M0 microcontroller
FT D R A
D R A
D R A FT D R FT
[2] [3] [4] [5] [6] [7] [8]
The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 5.
D
R
The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors. See Figure 5. The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the ideal curve. See Figure 5. The gain error (EG) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset error, and the straight line which fits the ideal transfer curve. See Figure 5. The absolute error (ET) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated ADC and the ideal transfer curve. See Figure 5. Tamb = 25 C; maximum sampling frequency fs = 4.5 MHz and analog input capacitance Cia = 1 pF. Input resistance Ri depends on the sampling frequency fs: Ri = 1 / (fs x Cia).
R A FT D R
R A F D R A FT D A FT D R A
A
FT R
A
FT
D
LPC1102
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D
D
D R A FT
D R A FT
NXP Semiconductors
LPC1102
FT FT D D R R A A FT FT D D R R A A FT FT D D
D R A
R
R A
A FT
32-bit ARM Cortex-M0 microcontroller
FT D R R
offset error EO 1023
D R A
D R A FT D R FT D R A
R A FT
gain error EG
A
A
FT
F
D
D R A FT D
R A FT D A FT D R
1022
R A
1021
1020
1019
1018
(2)
7 code out 6
(1)
5
(5)
4
(4)
3
(3)
2
1
1 LSB (ideal) 1018 1019 1020 1021 1022 1023 1024
0 1 offset error EO 2 3 4 5 6 7 VIA (LSBideal)
1 LSB =
VDD - VSS 1024
002aaf426
(1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (ED). (4) Integral non-linearity (EL(adj)). (5) Center of a step of the actual transfer curve.
Fig 5.
ADC characteristics
LPC1102
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D
D R A FT
D R A FT
NXP Semiconductors
LPC1102
FT FT D D R R A A FT FT D D R R A A FT FT D D
D R A
R
R A
A FT
32-bit ARM Cortex-M0 microcontroller
FT D R A
D R A
D R A FT D R FT
9.1 BOD static characteristics
Table 7. BOD static characteristics[1] Tamb = 25 C. Symbol Vth Parameter threshold voltage Conditions interrupt level 0 assertion de-assertion interrupt level 1 assertion de-assertion interrupt level 2 assertion de-assertion interrupt level 3 assertion de-assertion reset level 0 assertion de-assertion reset level 1 assertion de-assertion reset level 2 assertion de-assertion reset level 3 assertion de-assertion
[1]
D
R
R A FT D R
R A F D R A FT
A FT A FT
Min -
Typ 1.65 1.80 2.22 2.35 2.52 2.66 2.80 2.90 1.46 1.63 2.06 2.15 2.35 2.43 2.63 2.71
Max -
Unit V V V V V V V V V V V V V V V V
D
Interrupt levels are selected by writing the level value to the BOD control register BODCTRL, see LPC111x user manual.
D R A FT D
R A
9.2 Power consumption
Power measurements in Active, Sleep, and Deep-sleep modes were performed under the following conditions (see LPC111x user manual):
* Configure all pins as GPIO with pull-up resistor disabled in the IOCONFIG block. * Configure GPIO pins as outputs using the GPIOnDIR registers. * Write 0 to all GPIOnDATA registers to drive the outputs LOW.
LPC1102
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D
D
D R A FT
D R A FT
NXP Semiconductors
LPC1102
FT FT D D R R A A FT FT D D R R A A FT FT D D
D R A
R
R A
A FT
32-bit ARM Cortex-M0 microcontroller
FT D R
001aac984
D R A
D R A FT D R FT D A
R
R A FT
R A F
A FT
X X (X) X
D
D R A FT D
R A FT D A FT D R R
X
X

X X X X X (X) X
A
X
X
Conditions: Tamb = 25 C; active mode entered executing code while(1){} from flash; all peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL= 0x1F); all peripheral clocks disabled; internal pull-up resistors disabled; BOD disabled. (1) System PLL disabled; IRC enabled. (2) System PLL enabled; IRC disabled.
Fig 6.
Active mode: Typical supply current IDD versus supply voltage VDD for different system clock frequencies
X X (X) X
001aac984
X
X

X X X X X (X) X
X
X
Conditions: VDD = 3.3 V; active mode entered executing code while(1){} from flash; all peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL= 0x1F); all peripheral clocks disabled; internal pull-up resistors disabled; BOD disabled. (1) System PLL disabled; IRC enabled. (2) System PLL enabled; IRC disabled.
Fig 7.
Active mode: Typical supply current IDD versus temperature for different system clock frequencies
LPC1102
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D
D R A FT
D R A FT
NXP Semiconductors
LPC1102
FT FT D D R R A A FT FT D D R R A A FT FT D D
D R A
R
R A
A FT
32-bit ARM Cortex-M0 microcontroller
FT D R
001aac984
D R A
D R A FT D R FT D A
R
R A FT
R A F
A FT
X X (X) X
D
D R A FT D
R A FT D A FT D R R
X
X

X X X X X (X) X
A
X
X
Conditions: VDD = 3.3 V; sleep mode entered from flash; all peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL= 0x1F); all peripheral clocks disabled; internal pull-up resistors disabled; BOD disabled. (1) System PLL disabled; IRC enabled. (2) System PLL enabled; IRC disabled.
Fig 8.
Sleep mode: Typical supply current IDDversus temperature for different system clock frequencies
X X (X) X
001aac984
X
X

X X X X X (X) X
X
X
Conditions: BOD disabled; all oscillators and analog blocks disabled in the PDSLEEPCFG register (PDSLEEPCFG = 0x0000 18FF).
Fig 9.
Deep-sleep mode: Typical supply current IDD versus temperature for different supply voltages VDD
LPC1102
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D
D R A FT
D R A FT
NXP Semiconductors
LPC1102
FT FT D D R R A A FT FT D D R R A A FT FT D D
D R A
R
R A
A FT
32-bit ARM Cortex-M0 microcontroller
FT D R A
D R A
D R A FT D R FT
9.3 Electrical pin characteristics
15 IOL (mA) 10 T = 85 C 25 C -40 C
D
R
002aae991
R A FT D R
R A F D R A FT
A FT A FT D R A
D FT D R A
5
0 0 0.2 0.4 VOL (V) 0.6
Conditions: VDD = 3.3 V; standard port pins.
Fig 10. Typical LOW-level output current IOL versus LOW-level output voltage VOL
3.6 VOH (V) 3.2
002aae992
T = 85 C 25 C -40 C
2.8
2.4
2 0 8 16 IOH (mA) 24
Conditions: VDD = 3.3 V; standard port pins.
Fig 11. Typical HIGH-level output voltage VOH versus HIGH-level output source current IOH
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D
D R A FT
D R A FT
NXP Semiconductors
LPC1102
FT FT D D R R A A FT FT D D R R A A FT FT D D
D R A
R
R A
A FT
32-bit ARM Cortex-M0 microcontroller
FT D R
002aae988
D R A
D R A FT D R FT D A
R
R A FT
R A F
A FT
10 Ipu (A) -10
D
D R A FT D
R A FT D A FT D R A R
-30 T = 85 C 25 C -40 C
-50
-70
0
1
2
3
4 VI (V)
5
Conditions: VDD = 3.3 V; standard port pins.
Fig 12. Typical pull-up current Ipu versus input voltage VI
80 Ipd (A) 60 T = 85 C 25 C -40 C
002aae989
40
20
0 0 1 2 3 4 VI (V) 5
Conditions: VDD = 3.3 V; standard port pins.
Fig 13. Typical pull-down current Ipd versus input voltage VI
LPC1102
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D
D R A FT
D R A FT
NXP Semiconductors
LPC1102
FT FT D D R R A A FT FT D D R R A A FT FT D D
D R A
R
R A
A FT
32-bit ARM Cortex-M0 microcontroller
FT D R A
D R A
D R A FT D R FT
10. Dynamic characteristics
10.1 Flash memory
Table 8. Flash characteristics Tamb = -40 C to +85 C, unless otherwise specified. Symbol Nendu tret ter Parameter endurance retention time erase time powered unpowered sector or multiple consecutive sectors
[2]
D
R
R A FT D R
R A F D R A FT
A FT A FT D R A
D FT D R
Conditions
[1]
Min 10000 10 20 95
Typ 100
Max 105
Unit cycles years years ms
A
tprog
[1] [2]
programming time
0.95
1
1.05
ms
Number of program/erase cycles. Programming times are given for writing 256 bytes from RAM to the flash. Data must be written to the flash in blocks of 256 bytes.
10.2 External clock
Table 9. Dynamic characteristic: external clock Tamb = -40 C to +85 C; VDD over specified ranges.[1] Symbol fosc Tcy(clk) tCHCX tCLCX tCLCH tCHCL
[1] [2]
Parameter oscillator frequency clock cycle time clock HIGH time clock LOW time clock rise time clock fall time
Conditions
Min 1 40 Tcy(clk) x 0.4 Tcy(clk) x 0.4 -
Typ[2] -
Max 25 1000 5 5
Unit MHz ns ns ns ns ns
Parameters are valid over operating temperature range unless otherwise specified. Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages.
tCHCL
tCLCX Tcy(clk)
tCHCX tCLCH
002aaa907
Fig 14. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV)
LPC1102
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D
D R A FT
D R A FT
NXP Semiconductors
LPC1102
FT FT D D R R A A FT FT D D R R A A FT FT D D
D R A
R
R A
A FT
32-bit ARM Cortex-M0 microcontroller
FT D R A
D R A
D R A FT D R FT
10.3 Internal oscillators
Table 10. Dynamic characteristic: internal oscillators Tamb = -40 C to +85 C; 2.7 V VDD 3.6 V.[1] Symbol fosc(RC)
[1] [2]
D
R
R A FT D R
Typ[2] 12
R A F D R A FT
A FT A FT
Parameter
Conditions
Min 11.88
Max 12.12
Unit
D
D R A
internal RC oscillator frequency -
MHz
FT D
Parameters are valid over operating temperature range unless otherwise specified. Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages.
R A
X X (X) X
001aac984
X
X

X X X X X (X) X
X
X
Conditions: Frequency values are typical values. 12 MHz 1% accuracy is guaranteed for 2.7 V VDD 3.6 V and Tamb = -40 C to +85 C. Variations between parts may cause the IRC to fall outside the 12 MHz 1% accuracy specification for voltages below 2.7 V.
Fig 15. Internal RC oscillator frequency vs. temperature Table 11. fosc Dynamic characteristics: Watchdog oscillator Conditions
[2][3]
Symbol Parameter
Min -
Typ[1] 7.8 1700
Max -
Unit kHz kHz
internal oscillator DIVSEL = 0x1F, FREQSEL = 0x1 frequency in the WDTOSCCTRL register; DIVSEL = 0x00, FREQSEL = 0xF in the WDTOSCCTRL register
[2][3]
[1] [2] [3]
Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. The typical frequency spread over processing and temperature (Tamb = -40 C to +85 C) is 40%. See the LPC111x user manual.
LPC1102
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D
D
D R A FT
D R A FT
NXP Semiconductors
LPC1102
FT FT D D R R A A FT FT D D R R A A FT FT D D
D R A
R
R A
A FT
32-bit ARM Cortex-M0 microcontroller
FT D R A
D R A
D R A FT D R FT
10.4 I/O pins
Table 12. Dynamic characteristic: I/O pins[1] Tamb = -40 C to +85 C; 3.0 V VDD 3.6 V. Symbol tr Parameter rise time Conditions pin configured as output pin configured as output Min 3.0 Typ -
D
R
Max 5.0
R A FT D R
R A F D R A FT
A FT
Unit ns
A FT D R A
D FT D R A
tf
fall time
2.5
-
5.0
ns
[1]
Applies to standard port pins and RESET pin.
10.5 SPI interfaces
Table 13. Symbol Tcy(clk) tDS Dynamic characteristics of SPI pins in SPI mode Parameter clock cycle time data set-up time Conditions when only receiving when only transmitting in SPI mode 2.4 V VDD 3.6 V 2.0 V VDD < 2.4 V 1.8 V VDD < 2.0 V tDH tv(Q) th(Q) Tcy(PCLK) tDS tDH tv(Q) th(Q)
[1]
[2] [2] [2] [2] [2] [1] [1] [2]
Min 40 27.8 15 20 24 0 0 20
Typ -
Max -
Unit ns ns ns ns
SPI master (in SPI mode)
-
10 3 x Tcy(PCLK) + 11 2 x Tcy(PCLK) + 5
ns ns ns ns ns ns ns ns ns
data hold time
in SPI mode
data output valid time in SPI mode data output hold time in SPI mode PCLK cycle time data set-up time data hold time in SPI mode in SPI mode
SPI slave (in SPI mode)
[3][4] [3][4] [3][4] [3][4]
0 3 x Tcy(PCLK) + 4 -
data output valid time in SPI mode data output hold time in SPI mode
Tcy(clk) = (SSPCLKDIV x (1 + SCR) x CPSDVSR) / fmain. The clock cycle time derived from the SPI bit rate Tcy(clk) is a function of the main clock frequency fmain, the SPI peripheral clock divider (SSPCLKDIV), the SPI SCR parameter (specified in the SSP0CR0 register), and the SPI CPSDVSR parameter (specified in the SPI clock prescale register). Tamb = -40 C to 85 C. Tcy(clk) = 12 x Tcy(PCLK). Tamb = 25 C; for normal voltage supply range: VDD = 3.3 V.
[2] [3] [4]
LPC1102
All information provided in this document is subject to legal disclaimers.
(c) NXP B.V. 2010. All rights reserved.
Objective data sheet
Rev. 00 -- 23 June 2010
28 of 38
D
D
D R A FT
D R A FT
NXP Semiconductors
LPC1102
FT FT D D R R A A FT FT D D R R A A FT FT D D
D R A
R
R A
A FT
32-bit ARM Cortex-M0 microcontroller
FT D R R A
D R A
D R A FT D R FT D R
R A FT FT
A
A F
Tcy(clk)
tclk(H)
tclk(L)
D
D R A FT
R A FT
SCK (CPOL = 0)
D
D R A FT
SCK (CPOL = 1) tv(Q) MOSI DATA VALID DATA VALID tDS MISO DATA VALID tDH DATA VALID CPHA = 1 th(Q)
D R A
tv(Q) MOSI DATA VALID DATA VALID tDS MISO DATA VALID tDH DATA VALID
th(Q)
CPHA = 0
002aae829
Fig 16. SPI master timing in SPI mode
LPC1102
All information provided in this document is subject to legal disclaimers.
(c) NXP B.V. 2010. All rights reserved.
Objective data sheet
Rev. 00 -- 23 June 2010
29 of 38
D
D
D R A FT
D R A FT
NXP Semiconductors
LPC1102
FT FT D D R R A A FT FT D D R R A A FT FT D D
D R A
R
R A
A FT
32-bit ARM Cortex-M0 microcontroller
FT D R R A
D R A
D R A FT D R FT D R
R A FT FT
A
A F
Tcy(clk)
tclk(H)
tclk(L)
D
D R A
R A FT
SCK (CPOL = 0)
FT D R A
D FT
SCK (CPOL = 1) tDS MOSI DATA VALID tv(Q) MISO DATA VALID DATA VALID tDH DATA VALID th(Q) CPHA = 1
D R A
tDS MOSI DATA VALID tv(Q) MISO DATA VALID
tDH
DATA VALID th(Q) DATA VALID CPHA = 0
002aae830
Fig 17. SPI slave timing in SPI mode
LPC1102
All information provided in this document is subject to legal disclaimers.
(c) NXP B.V. 2010. All rights reserved.
Objective data sheet
Rev. 00 -- 23 June 2010
30 of 38
D
D
D R A FT
D R A FT
NXP Semiconductors
LPC1102
FT FT D D R R A A FT FT D D R R A A FT FT D D
D R A
R
R A
A FT
32-bit ARM Cortex-M0 microcontroller
FT D R A
D R A
D R A FT D R FT
11. Application information
11.1 ADC usage notes
D
R
The following guidelines show how to increase the performance of the ADC in a noisy environment beyond the ADC specifications listed in Table 6:
* The ADC input trace must be short and as close as possible to the LPC1102 chip. * The ADC input traces must be shielded from fast switching digital signals and noisy
power supply lines.
* Because the ADC and the digital core share the same power supply, the power supply
line must be adequately filtered.
* To improve the ADC performance in a very noisy environment, put the device in Sleep
mode during the ADC conversion.
R A FT D R
R A F D R A FT
A FT A FT D R A
D FT D R A
11.2 XTAL input
The input voltage to the on-chip oscillators is limited to 1.8 V. If the oscillator is driven by a clock in slave mode, it is recommended that the input be coupled through a capacitor with Ci = 100 pF. To limit the input voltage to the specified range, choose an additional capacitor to ground Cg which attenuates the input voltage by a factor Ci/(Ci + Cg). In slave mode, a minimum of 200 mV(RMS) is needed.
LPC1xxx
XTALIN
Ci 100 pF Cg
002aae788
Fig 18. Slave mode operation of the on-chip oscillator
In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF (Figure 18), with an amplitude between 200 mV(RMS) and 1000 mV(RMS). This corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V.
11.3 Standard I/O pad configuration
Figure 19 shows the possible pin modes for standard I/O pins with analog input function:
* * * * *
LPC1102
Digital output driver Digital input: Pull-up enabled/disabled Digital input: Pull-down enabled/disabled Digital input: Repeater mode enabled/disabled Analog input
All information provided in this document is subject to legal disclaimers.
(c) NXP B.V. 2010. All rights reserved.
Objective data sheet
Rev. 00 -- 23 June 2010
31 of 38
D
D
D R A FT
D R A FT
NXP Semiconductors
LPC1102
FT FT D D R R A A FT FT D D R R A A FT FT D D
D R A
R
R A
A FT
32-bit ARM Cortex-M0 microcontroller
FT D R
VDD ESD
D R A
D R A FT D R FT D A
R
R A FT D R
R A F D R A FT
A FT A FT
output enable pin configured as digital output driver output
D
PIN ESD
D R A FT D
R A
VDD weak pull-up pull-up enable repeater mode enable pull-down enable weak pull-down
VSS
pin configured as digital input
data input
select analog input pin configured as analog input analog input
002aaf304
Fig 19. Standard I/O pad configuration
11.4 Reset pad configuration
VDD VDD VDD
Rpu
ESD
reset
20 ns RC GLITCH FILTER
PIN
ESD
VSS
002aaf274
Fig 20. Reset pad configuration
LPC1102
All information provided in this document is subject to legal disclaimers.
(c) NXP B.V. 2010. All rights reserved.
Objective data sheet
Rev. 00 -- 23 June 2010
32 of 38
D
D
D R A FT
D R A FT
NXP Semiconductors
LPC1102
FT FT D D R R A A FT FT D D R R A A FT FT D D
D R A
R
R A
A FT
32-bit ARM Cortex-M0 microcontroller
FT D R A
D R A
D R A FT D R FT
12. Package outline
D
R
R A FT D R
R A F D R A FT
A FT A FT D R A
D FT D R A
Fig 21. Package outline (WLCSP16)
LPC1102 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved.
Objective data sheet
Rev. 00 -- 23 June 2010
33 of 38
D
D
D R A FT
D R A FT
NXP Semiconductors
LPC1102
FT FT D D R R A A FT FT D D R R A A FT FT D D
D R A
R
R A
A FT
32-bit ARM Cortex-M0 microcontroller
FT D R A
D R A
D R A FT D R FT
13. Abbreviations
Table 14. Acronym ADC AHB AMBA APB BOD GPIO PLL RC SPI SSI SSP TTL UART Abbreviations Description Analog-to-Digital Converter Advanced High-performance Bus Advanced Microcontroller Bus Architecture Advanced Peripheral Bus BrownOut Detection General Purpose Input/Output Phase-Locked Loop Resistor-Capacitor Serial Peripheral Interface Serial Synchronous Interface Synchronous Serial Port Transistor-Transistor Logic Universal Asynchronous Receiver/Transmitter
D
R
R A FT D R
R A F D R A FT
A FT A FT D R A
D FT D R A
LPC1102
All information provided in this document is subject to legal disclaimers.
(c) NXP B.V. 2010. All rights reserved.
Objective data sheet
Rev. 00 -- 23 June 2010
34 of 38
D
D
D R A FT
D R A FT
NXP Semiconductors
LPC1102
FT FT D D R R A A FT FT D D R R A A FT FT D D
D R A
R
R A
A FT
32-bit ARM Cortex-M0 microcontroller
FT D R A
D R A
D R A FT D R FT
14. Revision history
Table 15. Revision history Release date Data sheet status Objective data sheet Change notice Supersedes Document ID LPC1102 v. 0.04
D
R
LPC1102 v. 0.03
R A FT D R
R A F D R A FT
A FT A FT D R A
D FT D R A
LPC1102
All information provided in this document is subject to legal disclaimers.
(c) NXP B.V. 2010. All rights reserved.
Objective data sheet
Rev. 00 -- 23 June 2010
35 of 38
D
D
D R A FT
D R A FT
NXP Semiconductors
LPC1102
FT FT D D R R A A FT FT D D R R A A FT FT D D
D R A
R
R A
A FT
32-bit ARM Cortex-M0 microcontroller
FT D R A
D R A
D R A FT D R FT
15. Legal information
15.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
D
R
R A FT D R
R A F D R A FT
A FT A FT D R
D
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
A FT D R A
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification -- The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.
malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on a weakness or default in the customer application/use or the application/use of customer's third party customer(s) (hereinafter both referred to as "Application"). It is customer's sole responsibility to check whether the NXP Semiconductors product is suitable and fit for the Application planned. Customer has to do all necessary testing for the Application in order to avoid a default of the Application and the product. NXP Semiconductors does not accept any liability in this respect. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer's general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. Non-automotive qualified products -- Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors' warranty of the
(c) NXP B.V. 2010. All rights reserved.
15.3 Disclaimers
Limited warranty and liability -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors' aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or
LPC1102
All information provided in this document is subject to legal disclaimers.
Objective data sheet
Rev. 00 -- 23 June 2010
36 of 38
D
D
D R A FT
D R A FT
NXP Semiconductors
LPC1102
FT FT D D R R A A FT FT D D R R A A FT FT D D
D R A
R
R A
A FT
32-bit ARM Cortex-M0 microcontroller
FT D R A
D R A
D R A FT D R FT
product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors' specifications such use shall be solely at customer's own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors' standard warranty and NXP Semiconductors' product specifications.
15.4 Trademarks
D
R
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
R A FT D R
R A F D R A FT D FT D R
A FT R A A FT D
16. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
A
LPC1102
All information provided in this document is subject to legal disclaimers.
(c) NXP B.V. 2010. All rights reserved.
Objective data sheet
Rev. 00 -- 23 June 2010
37 of 38
D
D
D R A FT
D R A FT
NXP Semiconductors
LPC1102
FT FT D D R R A A FT FT D D R R A A FT FT D D
D R A
R
R A
A FT
32-bit ARM Cortex-M0 microcontroller
FT D R A
D R A
D R A FT D R FT
17. Contents
1 2 3 4 4.1 5 6 6.1 6.2 7 7.1 7.2 7.3 7.4 7.5 7.5.1 7.5.2 7.6 7.7 7.7.1 7.8 7.8.1 7.9 7.9.1 7.10 7.10.1 7.11 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 6 ARM Cortex-M0 processor . . . . . . . . . . . . . . . . 6 On-chip flash program memory . . . . . . . . . . . . 6 On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . . 6 Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Nested Vectored Interrupt Controller (NVIC) . . 7 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . . 8 IOCONFIG block . . . . . . . . . . . . . . . . . . . . . . . 8 Fast general purpose parallel I/O . . . . . . . . . . . 8 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 SPI serial I/O controller. . . . . . . . . . . . . . . . . . . 9 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 10-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 General purpose external event counter/timers . . 10 7.11.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 7.12 System tick timer . . . . . . . . . . . . . . . . . . . . . . 10 7.13 Watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . 10 7.13.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 7.14 Clocking and power control . . . . . . . . . . . . . . 11 7.14.1 Crystal oscillators . . . . . . . . . . . . . . . . . . . . . . 11 7.14.1.1 Internal RC oscillator . . . . . . . . . . . . . . . . . . . 12 7.14.1.2 Watchdog oscillator . . . . . . . . . . . . . . . . . . . . 12 7.14.2 System PLL . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7.14.3 Wake-up process . . . . . . . . . . . . . . . . . . . . . . 13 7.14.4 Power control . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.14.4.1 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.14.4.2 Deep-sleep mode . . . . . . . . . . . . . . . . . . . . . . 13 7.15 System control . . . . . . . . . . . . . . . . . . . . . . . . 14 7.15.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.15.2 Brownout detection . . . . . . . . . . . . . . . . . . . . . 14 7.15.3 Code security (Code Read Protection - CRP) 14 7.15.4 APB interface . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.15.5 AHBLite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.15.6 7.15.7 7.16 8 9 9.1 9.2 9.3 10 10.1 10.2 10.3 10.4 10.5 11 11.1 11.2 11.3 11.4 12 13 14 15 15.1 15.2 15.3 15.4 16 17
D
R
External interrupt inputs . . . . . . . . . . . . . . . . . Memory mapping control . . . . . . . . . . . . . . . . Emulation and debugging . . . . . . . . . . . . . . . Limiting values . . . . . . . . . . . . . . . . . . . . . . . . Static characteristics . . . . . . . . . . . . . . . . . . . BOD static characteristics . . . . . . . . . . . . . . . Power consumption . . . . . . . . . . . . . . . . . . . Electrical pin characteristics. . . . . . . . . . . . . . Dynamic characteristics. . . . . . . . . . . . . . . . . Flash memory . . . . . . . . . . . . . . . . . . . . . . . . External clock. . . . . . . . . . . . . . . . . . . . . . . . . Internal oscillators . . . . . . . . . . . . . . . . . . . . . I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI interfaces. . . . . . . . . . . . . . . . . . . . . . . . . Application information . . . . . . . . . . . . . . . . . ADC usage notes. . . . . . . . . . . . . . . . . . . . . . XTAL input . . . . . . . . . . . . . . . . . . . . . . . . . . . Standard I/O pad configuration . . . . . . . . . . . Reset pad configuration . . . . . . . . . . . . . . . . . Package outline. . . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
R A FT D R
R A F D R A FT D FT D R A
A FT
15 15 15 16 17 21 21 24 26 26 26 27 28 28 31 31 31 31 32 33 34 35 36 36 36 36 37 37 38
A
FT
D
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(c) NXP B.V. 2010.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 23 June 2010 Document identifier: LPC1102

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